1、题目This is the fourth component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.You may wish to do FSM: Enable shift register and FSM: Sequence recognizer first.We want to create a timer that:is started when a particular pattern (1101) is detected,shifts in 4 more bits to determine the duration to delay,waits for the counters to finish counting, andnotifies the user and waits for the user to acknowledge the timer.In this problem, implement just the finite-state machine that controls the timer. The data path (counters and some comparators) are not included here.The serial data is available on the data input pin. When the pattern 1101 is received, the state machine must then assert output shift_ena for exactly 4 clock cycles.After that, the state machine asserts its counting output to indicate it is waiting for the counters, and waits until input done_counting is high.At that point, the state machine must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).The state machine should reset into a state where it begins searching for the input sequence 1101.Here is an example of the expected inputs and outputs. The x states may be slightly confusing to read. They indicate that the FSM should not care about that particular input signal in that cycle. For example, once a 1101 pattern is detected, the FSM no longer looks at the data input until it resumes searching after everything else is done.豆包翻译这是五道配套练习题的第 4 题整套习题会利用多个小型电路搭建一套复杂计数器你可以查看最终习题了解整体整体架构。 建议你先完成两道前置习题【有限状态机移位寄存器使能】与【有限状态机序列检测器】。我们需要搭建一个定时器工作流程如下一旦检测到特定比特序列1101定时器启动再移入 4 个比特位用来确定定时延时的时长等待计数器完成计数向使用者发出通知并等待使用者对定时器进行应答确认。在本题中只需要实现控制定时器的有限状态机计数器、比较器这类数据通路电路不需要编写。串行输入比特流由引脚data输入一旦检测到1101序列状态机必须将输出shift_ena持续拉高恰好 4 个时钟周期。 4 个移位周期结束后状态机拉高输出counting表示正在等待计数器工作完成一直等待到输入信号done_counting变为高电平。 当done_counting拉高后状态机拉高done通知用户定时器计时结束随后保持等待直到输入ack变为高电平之后状态机复位重新开始搜寻起始序列1101。状态机复位后会进入初始状态该状态的工作内容为持续搜寻输入序列1101。题目附带了一组输入输出时序示例。图中标注的无关态 “x” 容易造成阅读困扰它代表该时钟周期内状态机无需关心对应输入信号。 举例说明一旦检测到1101序列在整轮流程全部结束、重新回到搜寻阶段前状态机不再读取data输入。2、分析思路寻找输入的序列“1101”找到后shift_data拉高4个时钟周期拉低shift_data拉低后counting开始计数当输入done_counting为高时counting停止计数并清零。done_counting拉高一个时钟周期后done拉高直到ack为高时done拉低。而ack只拉高了一个时钟周期便重新开始检测“1101”序列IDEL0,初始状态考虑输入dataBIT11,bit1状态考虑输入dataBIT22,bit2状态考虑输入dataBIT33,bit3状态考虑输入dataBIT44,bit4状态后续看输入时钟DELAY_45,延时4个时钟周期结束的状态后续看输入done_countingFIANL_DONE6;计数结束的状态后续看输入ack3、代码module top_module ( input clk , input reset, // Synchronous reset input data , output shift_ena, output counting, input done_counting, output done, input ack ); parameter IDEL0,BIT11,BIT22,BIT33,BIT44,DELAY_45,FIANL_DONE6; reg [3:0] curr_state, next_state; always (posedge clk) begin if (reset) begin curr_state IDEL; end else begin curr_state next_state; end end reg [3:0]cnt; always (posedge clk) begin if (reset) begin cnt 4d0; end else if (curr_stateBIT4) begin//进入此状态后再计数4个时钟周期 if (cnt 4d3)begin cnt 4d0;//居然不能等于cnt end else begin cnt cnt 4d1; end end end always (*) begin case (curr_state) IDEL: next_state data?BIT1:IDEL; BIT1: next_state data?BIT2:IDEL;//bit11看下一bit BIT2: next_state data?BIT2:BIT3;//bit11看下一bit BIT3: next_state data?BIT4:IDEL;//bit10看下一bit BIT4: next_state (cnt4d3)?DELAY_4:BIT4;//bit11看四个时钟的延时是否完成 DELAY_4: next_state (done_counting1b1)?FIANL_DONE:DELAY_4;//延时结束看计时器是否完成计数 FIANL_DONE: next_state (ack1b1)?IDEL:FIANL_DONE;//已完成计数通知用户等待用户确认 default: next_stateIDEL; endcase end assign shift_ena(curr_stateBIT4); assign counting(curr_stateDELAY_4); assign done(curr_stateFIANL_DONE); endmodule